FPGA devices combine ASIC's high performance and microprocessor flexibility, not only with rich logic resources, but also for easy and flexible configuration. Active configuration Although the configuration is fast, easy to implement, but did not play a flexible FPGA configuration features, suitable for FPGA applications for a single application, and large-capacity configuration of the chip and its occupied circuit board area also brought a higher The passive configuration method requires the use of external control units to generate configuration timing, the implementation is generally more complex, and in the current common program, often due to interface rate limit  or the use of microprocessors involved in data transmission and other reasons, resulting in configuration The speed is not high.
USB2.0 protocol in the current PC peripheral interface program is very popular, it supports high-speed, multi-channel, multi-type data transmission, you can easily build a high-performance data transmission channel and flexible control channel.
This paper presents a USB interface based FPGA SelectMap (parallel passive) configuration of the program, not only has a passive configuration flexibility, low design cost characteristics, and to achieve a simple, fast configuration. (XC3S5000) as the configuration target, the use of Cypress EZ-USB FX2LP as a USB device chip, and use its internal large-capacity endpoint FIFO, under the control of the GPIF state machine, the realization of the program, the use of the Xilinx Spartan3 series of the largest capacity of 500 million gate FPGA (XC3S5000) A high-performance configuration data transmission channel. The configuration process is controlled by the designed USB request. This configuration has the advantages of simple development, low cost, fast speed and flexible use, and has strong practicability.
2. The overall design of the system
The overall design of the system
As shown in Figure 1, the system uses the USB channel to connect the host computer and EZ-USB. EZ-USB is a high-speed USB peripheral chip, which supports the USB protocol described in all four transmission modes, and has a 64Byte control transmission dedicated endpoint, 2 cache for the 64Byte ordinary endpoint and 4 cache up to 1KB , And can be four times the buffer of large data transfer from the endpoint to the peripheral (FPGA) process, if the use of USB device chip embedded 8051 MCU transfer, then the fastest 8 clock cycles to transmit a byte of data , the 8051 clock cycle in the case of 48MHz, the transmission speed of 6MB / s, much smaller than the USB channel transmission rate, will become a bottleneck and can not play the USB transmission channel high transmission rate advantage; and if the bit width For the 8bit FIFO to transmit, then the fastest case, each clock cycle can transmit a byte of data . In EZ-USB, the large endpoint cache can be used as the endpoint FIFO directly connected to the FPGA configuration data input port to form a high-speed transmission channel, the endpoint FIFO read and write timing can be generated by the EZ-USB embedded GPIF  (General Programmable Interface) , MCU can not participate in the endpoint to the FPGA data transfer, only play the role of configuration and control, FIFO bit width of 8bit, GPIF clock frequency of 48MHz, the transmission rate of 48MB / s, so the data from the endpoint to the FPGA The transmission speed exceeds the host backup computer to usb windows 8 to the endpoint of the USB interrupt transmission pipeline maximum speed, not the USB transmission channel constitutes a bottleneck.
3. Configuration timing occurs
The configuration data needs to be written to the FPGA under the configuration timing . GPIF is a programmable state machine that can acquire the status of five input pins (RDY) and generate any timing through the five output pins (CTL), so it can be used to generate FPGA timing. Table 1 shows the FPGA in SelectMap mode, the role of the configuration pin , as shown in Figure 1, CCLK connection EZ-USB interface clock IFCLK, D [7: 0] connection endpoint FIFO, other configuration pin Connect the RDY and CTL pins of the GPIF state machine. In order to ensure that the input of each pin has sufficient setup time for FPGA sampling, the FPGA clock input should be inverted with the internal clock of the GPIF.
This design uses a control endpoint (endpoint 0) and a large endpoint (endpoint 2) to transfer data. Where the control endpoint is necessary for all USB devices and is used to transfer USB requests and associated data when the device is enumerated. In this design, the control endpoint is also used to transfer specially designed USB vendor requests to control the configuration process, Configuration status. The large endpoint is used to transmit the configuration data. Because the configuration data needs timely and unmistakable transmission, it can use the interrupt transmission mode which can guarantee the transmission accuracy and the maximum delay at the same time, and set the endpoint cache to 1KB, 4 times the buffer, the maximum transmission interval For a micro frame (125us), and each transmission interval transmission of three payload 1KB packet (the last packet load may be less than 1KB), so that the configuration data in the USB channel transfer rate can reach 3 * 1KB * (1 / 125us) = 24000KB / s.
Configure the pin description
According to the configuration timing of the design of the GPIF state machine state transition diagram shown in Figure 2. Configuration clock is 48MHz, so the PROG low pulse to maintain 25 clock cycles, the status of the opportunity FIFO according to the end of the FIFO full state control FPGA FPGA pin to ensure that the FPGA in the FIFO configuration data output data sampling, the data output Byte count reaches the FPGA configuration bitstream file when the byte value is stopped, the 5 million gate of the XC3S5000 is 13271936 bit .
Original link: http: //www.eeboard.com/news/selectmap/
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